The present invention relates to monolithic inductance-enhancing integrated circuits, to complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, to inductor assemblies, and to inductance-multiplying methods.
As integrated circuit devices continue to shrink in dimension, the demand to integrate different functionalities on the same integrated circuit die continues to grow. For example, portable wireless communication products have become high volume consumer devices. Some of these devices are now operating in the 1-2 GHz frequency range. There is, as a consequence, a demand to integrate RF front end circuits into high-yield silicon integrated circuit processes to allow a combination of analog, digital, and RF functions on the same integrated circuit die. Yet, some considerable difficulty has been experienced in attempts to fabricate inductors having high quality factors (Q) in silicon technology for RF circuits which are used in communications.
Attempts have been made to build high-Q inductors in silicon integrated circuit technology, but have yielded Q factors of only three to eight. This is undesirable in the context of RF circuit design at frequencies in the above-stated range, where required Q factors need to be typically in a range from between 5-20 for broad-band applications, and may have to be higher than 30 in narrow-band networks. Problems associated with the use of silicon technology in these scenarios, in part, is a result of the conductivity of silicon substrates which tends to induce losses. As frequencies approach the self resonant frequency, the inductance value decreases which is most undesirable. Losses in the conductive silicon substrates can be increased by the high dielectric constant of the insulators under the conductors and the relatively large values of stray capacitance coupling to the silicon substrate.
Some attempts have been made to provide oxide-encased, spiral-type inductors for silicon technology, with such encased inductors being disposed over a cavity which is etched into the silicon substrate. Others have attempted to provide higher-Q inductors in a five or six-level metal BiCMOS technology. The conductors in these instances are still encased in oxide but are far removed from the silicon substrate by virtue of a large number of insulator and metal levels. The number of these levels, however, is far in excess of the two to four levels commonly utilized in CMOS technology.
Other attempts have been made to provide higher-Q inductors through the use of long pad-to-pad wire bond techniques in BiCMOS technology in the design and fabrication of voltage controlled oscillators. Wire bond inductors have previously been used in a variety of applications as inductors and for impedance matching networks and, more recently, to create low impedance resonant connections from guard rings or bonding pads to ground planes. Having the conductor surrounded by air rather than an insulator serves to reduce losses from the conductive silicon substrates and yield high-Q values (11 to 15 at 1.8 GHz). However, having such long unsupported spans of wire, e.g. up to three millimeters in some cases, does not provide for good mechanical stability. In addition, there is no provision for, nor is there a possibility of, passivation in these structures. Air bridge or wire bond inductors might have very good high-Q values, but their characteristics typically tend to be subject to change in the event of severe mechanical shocks or abrasion. In addition, such structures are not suitably protected from corrosive environments.
Against the backdrop of these attempts, there continues to remain a need in silicon integrated circuit technologies for high-Q inductors with rigid and fixed mechanical characteristics. Such inductors are, or can be, used in the design and implementation of oscillators, tuned amplifiers, and in optimizing broad band amplifiers. These cannot be achieved by standard integrated circuit techniques, nor by air bridge and/or suspended metal conductors.
Inductance and Q-multipliers have been used previously in low frequency telephony circuits where operational amplifiers with a low unity gain corner frequency have been employed as the active gain elements. Examples of such are described in U.S. Pat. No. 4,767,980. More complicated feedback circuits employing operational amplifiers at low frequencies have been utilized to achieve Q-multiplier circuits. Such are described in U.S. Pat. Nos. 5,303,394, and 4,661,785. It is difficult, however, to fabricate operational amplifiers in CMOS technology with a high unity gain frequency.
Accordingly, this invention arose out of concerns associated with providing improved structures and methods for enhancing the inductive quality of integrated circuits. Particularly, this invention arose out of concerns associated with providing such structures and methods in the context of CMOS technology. Such structures preferably have high Q values at the frequencies of interest.
Monolithic inductance-enhancing integrated circuits, complementary metal oxide semiconductor (CMOS) inductance-enhancing integrated circuits, inductor assemblies, and inductance-multiplying methods are described.
In one embodiment, a monolithic inductance-enhancing integrated circuit comprises a transistor supported by a bulk monocrystalline silicon substrate. An inductor assembly is supported by the substrate and operably connected with the transistor in an inductance-enhancing circuit configuration having a quality factor (Q) greater than 10. In another embodiment, a complementary metal oxide semiconductor (CMOS), inductance-enhancing integrated circuit includes a field effect transistor supported over a silicon-containing substrate and having a gate, a source, and a drain. A first inductor is received within an insulative material layer over the substrate, and is connected to the gate. A second inductor is received within the insulative material layer and is connected to the source. The first and second inductors are arranged in a feedback loop which incorporates the field effect transistor. In another embodiment, an inductor assembly comprises a semiconductive silicon substrate having first and second spiral-type inductors received thereover to define first and second respective inductor levels which, preferably, have no more than four inductor or metal levels. In yet another embodiment, a monolithic substrate is provided having formed thereon integrated circuitry which is formed through complementary metal oxide semiconductor (CMOS) techniques and includes a field effect transistor and a pair of inductors. The transistor and inductor pair are arranged into a circuit configuration in which the field effect transistor can sample one of the pair of inductors and drive the other of the pair of inductors in a manner which effectively increases the inductance of the sampled inductor. In another embodiment, first and second spiral-type inductors are provided over a semiconductive substrate. The output of the first spiral-type inductor is sampled with a field effect transistor and the second spiral-type inductor is driven with the field effect transistor thereby increasing the inductance of the first spiral-type inductor.